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Proceedings Papers

Thermal Stress Simulation for 3D SiP With TSV Structure Under Unsteady Thermal Loads

Takahiro Kinoshita, Takashi Kawakami, Tomoya Sugiura, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii
Proc. ASME. InterPACK2015, Volume 2: Advanced Electronics and Photonics, Packaging Materials and Processing; Advanced Electronics and Photonics: Packaging, Interconnect and Reliability; Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales, V002T02A020, July 6–9, 2015
Publisher: American Society of Mechanical Engineers
Paper No: IPACK2015-48142
https://doi.org/10.1115/IPACK2015-48142
View Paper titled, Thermal Stress Simulation for 3D SiP With TSV Structure Under Unsteady Thermal Loads
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Topics: Simulation, Stress, Thermal stresses, Finite element methods, Heat, Temperature, Cooling, Damage, Packaging, Reliability
Proceedings Papers

Inelastic Thermal Stress Simulation for Si Chip and Insulator Around TSV in 3D SiP

Takahiro Kinoshita, Takashi Kawakami, Takeshi Wakamatsu, Shunpei Shima, Keiji Matsumoto, Sayuri Kohara, Fumiaki Yamada, Yasumitsu Orii
Proc. ASME. InterPACK2013, Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes, V001T04A009, July 16–18, 2013
Publisher: American Society of Mechanical Engineers
Paper No: IPACK2013-73151
https://doi.org/10.1115/IPACK2013-73151
View Paper titled, Inelastic Thermal Stress Simulation for Si Chip and Insulator Around TSV in 3D SiP
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Topics: Silicon chips, Simulation, Thermal stresses, Stress, Bending strength, Copper, Finite element methods, Yield stress, Brittleness, Elevations (Drawings)
Journal Articles

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Takahiro Kinoshita, Takashi Kawakami, Tatsuhiro Hori, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Photo Gallery
J. Electron. Packag. June 2012, 134(2): 020903.
https://doi.org/10.1115/1.4006515
Published Online: June 11, 2012
View Article titled, Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package
Open the PDF for Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package in another window
Topics: Finite element methods, Silicon, Silicon chips, Simulation, Stress, System-in-package, Thermal stresses, Temperature, Stress concentration
Proceedings Papers

Thermal Stress of Through Silicon Vias and Si Chips in 3D SiP

Takahiro Kinoshita, Takashi Kawakami, Tatsuhiro Hori, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada
Proc. ASME. InterPACK2011, ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1, 325-328, July 6–8, 2011
Publisher: American Society of Mechanical Engineers
Paper No: IPACK2011-52241
https://doi.org/10.1115/IPACK2011-52241
View Paper titled, Thermal Stress of Through Silicon Vias and Si Chips in 3D SiP
Open the PDF for Thermal Stress of Through Silicon Vias and Si Chips in 3D SiP in another window
Topics: Silicon, Silicon chips, Thermal stresses, Stress, Copper, Crystals, Damage, Reliability, Yield stress, Cycles